- 7. Platform Ports
- 7.34. Renesas R-Car
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“R-Car” is the nickname for Renesas’ system-on-chip (SoC) family forcar information systems designed for the next-generation of automotivecomputing for the age of autonomous vehicles.
The scalable R-Car hardware platform and flexible software platformcover the full product range, from the premium class to the entrylevel. Plug-ins are available for multiple open-source software tools.
7.34.1. Renesas R-Car Gen3 evaluation boards:
Standard | Low Cost Boards (LCB) | |
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R-Car H3 |
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R-Car M3-W |
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R-Car M3-N |
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R-Car V3M |
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R-Car V3H |
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R-Car D3 |
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The current TF-A port has been tested on the R-Car H3 Salvator-XSoc_id r8a7795 revision ES1.1 (uses a Secure Payload Dispatcher)
ARM CA57 (ARMv8) 1.5 GHz quad core, with NEON/VFPv4, L1$ I/D48K/32K, L2$ 2MBARM CA53 (ARMv8) 1.2 GHz quad core, with NEON/VFPv4, L1$ I/D 32K/32K,L2$ 512KMemory controller for LPDDR4-3200 4GB in 2 channels, each 64-bit wideTwo- and three-dimensional graphics engines,Video processing units,3 channels Display Output,6 channels Video Input,SD card host interface,USB3.0 and USB2.0 interfaces,CAN interfacesEthernet AVBPCI Express InterfacesMemories INTERNAL 384KB SYSTEM RAM DDR 4 GB LPDDR4 HYPERFLASH 64 MB HYPER FLASH (512 MBITS, 160 MHZ, 320 MBYTES/S) QSPI FLASH 16MB QSPI (128 MBITS,80 MHZ,80 MBYTES/S)1 HEADER QSPI MODULE EMMC 32 GB EMMC (HS400 240 MBYTES/S) MICROSD-CARD SLOT (SDR104 100 MBYTES/S)
7.34.2. Overview
On the rcar-gen3 the BOOTROM starts the cpu at EL3; for this port BL2will therefore be entered at this exception level (the Renesas’ ATFreference tree [1] resets into EL1 before entering BL2 - see itsbl2.ld.S)
BL2 initializes DDR (and on some platforms i2c to interface to thePMIC) before determining the boot reason (cold or warm).
During suspend all CPUs are switched off and the DDR is put in backupmode (some kind of self-refresh mode). This means that BL2 is alwaysentered in a cold boot scenario.
Once BL2 boots, it determines the boot reason, writes it to sharedmemory (BOOT_KIND_BASE) together with the BL31 parameters(PARAMS_BASE) and jumps to BL31.
To all effects, BL31 is as if it is being entered in reset mode sinceit still needs to initialize the rest of the cores; this is the reasonbehind using direct shared memory access to BOOT_KIND_BASE _and_PARAMS_BASE instead of using registers to get to those locations (seeel3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 usecase).
Depending on the boot reason BL31 initializes the rest of the cores:in case of suspend, it uses a MBOX memory region to recover theprogram counters.
7.34.3. How to build
The TF-A build options depend on the target board so you will have torefer to those specific instructions. What follows is customized tothe H3 SiP Salvator-X development system used in this port.
7.34.3.1. Build Tested:
RCAR_OPT=”LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1”MBEDTLS_DIR=$mbedtls_src
$ MBEDTLS_DIR=$mbedtls_src_tree make clean bl2 bl31 rcar_layout_tool PLAT=rcar ${RCAR_OPT} SPD=opteed
7.34.3.2. System Tested:
mbed_tls:git@github.com:ARMmbed/mbedtls.git [devel]
commit 552754a6ee82bab25d1bdf28c8261a4518e65e4dMerge: 68dbc94 f34a4c1Author: Simon Butcher <simon.butcher@arm.com>Date: Thu Aug 30 00:57:28 2018 +0100
optee_os:https://github.com/BayLibre/optee_os
Until it gets merged into OP-TEE, the port requires Renesas’Trusted Environment with a modification to support powermanagement.commit 80105192cba9e704ebe8df7ab84095edc2922f84
Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>Date: Thu Aug 30 16:49:49 2018 +0200plat-rcar: cpu-suspend: handle the power levelSigned-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
u-boot:The port has beent tested using mainline uboot.
commit 4cdeda511f8037015b568396e6dcc3d8fb41e8c0Author: Fabio Estevam <festevam@gmail.com>Date: Tue Sep 4 10:23:12 2018 -0300
linux:The port has beent tested using mainline kernel.
commit 7876320f88802b22d4e2daf7eb027dd14175a0f8Author: Linus Torvalds <torvalds@linux-foundation.org>Date: Sun Sep 16 11:52:37 2018 -0700Linux 4.19-rc4
7.34.3.3. TF-A Build Procedure
Fetch all the above 4 repositories.
Prepare the AARCH64 toolchain.
Build u-boot using r8a7795_salvator-x_defconfig.Result: u-boot-elf.srec
make CROSS_COMPILE=aarch64-linux-gnu- r8a7795_salvator-x_defconfigmake CROSS_COMPILE=aarch64-linux-gnu-
Build atfResult: bootparam_sa0.srec, cert_header_sa6.srec, bl2.srec, bl31.srec
RCAR_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"MBEDTLS_DIR=$mbedtls_src_tree make clean bl2 bl31 rcar \PLAT=rcar ${RCAR_OPT} SPD=opteed
Build optee-osResult: tee.srec
make -j8 PLATFORM="rcar" CFG_ARM64_core=y
7.34.3.4. Install Procedure
Boot the board in Mini-monitor mode and enable access to theHyperflash.
Use the XSL2 Mini-monitor utility to accept all the SREC asciitransfers over serial.
7.34.4. Boot trace
Notice that BL31 traces are not accessible via the console and that inorder to verbose the BL2 output you will have to compile TF-A withLOG_LEVEL=50 and DEBUG=1
Initial Program Loader(CA57) Rev.1.0.22NOTICE: BL2: PRR is R-Car H3 Ver.1.1NOTICE: BL2: Board is Salvator-X Rev.1.0NOTICE: BL2: Boot device is HyperFlash(80MHz)NOTICE: BL2: LCM state is CMNOTICE: AVS setting succeeded. DVFS_SetVID=0x53NOTICE: BL2: DDR1600(rev.0.33)NOTICE: [COLD_BOOT]NOTICE: ..0NOTICE: BL2: DRAM Split is 4chNOTICE: BL2: QoS is default setting(rev.0.37)NOTICE: BL2: Lossy Decomp areasNOTICE: Entry 0: DCMPAREACRAx:0x80000540 DCMPAREACRBx:0x570NOTICE: Entry 1: DCMPAREACRAx:0x40000000 DCMPAREACRBx:0x0NOTICE: Entry 2: DCMPAREACRAx:0x20000000 DCMPAREACRBx:0x0NOTICE: BL2: v2.0(release):v2.0-rc0-32-gbcda69aNOTICE: BL2: Built : 16:41:23, Oct 2 2018NOTICE: BL2: Normal bootINFO: BL2: Doing platform setupINFO: BL2: Loading image id 3NOTICE: BL2: dst=0xe6322000 src=0x8180000 len=512(0x200)NOTICE: BL2: dst=0x43f00000 src=0x8180400 len=6144(0x1800)WARNING: r-car ignoring the BL31 size from certificate,usingRCAR_TRUSTED_SRAM_SIZE insteadINFO: Loading image id=3 at address 0x44000000NOTICE: rcar_file_len: len: 0x0003e000NOTICE: BL2: dst=0x44000000 src=0x81c0000 len=253952(0x3e000)INFO: Image id=3 loaded: 0x44000000 - 0x4403e000INFO: BL2: Loading image id 4INFO: Loading image id=4 at address 0x44100000NOTICE: rcar_file_len: len: 0x00100000NOTICE: BL2: dst=0x44100000 src=0x8200000 len=1048576(0x100000)INFO: Image id=4 loaded: 0x44100000 - 0x44200000INFO: BL2: Loading image id 5INFO: Loading image id=5 at address 0x50000000NOTICE: rcar_file_len: len: 0x00100000NOTICE: BL2: dst=0x50000000 src=0x8640000 len=1048576(0x100000)INFO: Image id=5 loaded: 0x50000000 - 0x50100000NOTICE: BL2: Booting BL31INFO: Entry point address = 0x44000000INFO: SPSR = 0x3cdVERBOSE: Argument #0 = 0xe6325578VERBOSE: Argument #1 = 0x0VERBOSE: Argument #2 = 0x0VERBOSE: Argument #3 = 0x0VERBOSE: Argument #4 = 0x0VERBOSE: Argument #5 = 0x0VERBOSE: Argument #6 = 0x0VERBOSE: Argument #7 = 0x0U-Boot 2018.09-rc3-00028-g3711616 (Sep 27 2018 - 18:50:24 +0200)CPU: Renesas Electronics R8A7795 rev 1.1Model: Renesas Salvator-X board based on r8a7795 ES2.0+DRAM: 3.5 GiBFlash: 64 MiBMMC: sd@ee100000: 0, sd@ee140000: 1, sd@ee160000: 2Loading Environment from MMC... OKIn: serial@e6e88000Out: serial@e6e88000Err: serial@e6e88000Net: eth0: ethernet@e6800000Hit any key to stop autoboot: 0=>
